A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning

Multiplying delay-locked loops (MDLLs) have been shown to have improved jitter accumulation and tracking over VCO-based PLLs. By injecting the reference clock edge into the VCO at each reference cycle, an MDLL removes the accumulated jitter of the VCO. The principal challenge in MDLL design is to align the injected reference edge with the loop feedback signal. Timing mismatch between the reference edge and the VCO feedback edge, or offsets in the charge pump, would introduce a phase error in the injected edge. The error manifests as a period jitter or reference spur in the frequency domain. This effect limits the minimum jitter attained by the MDLL. In previously published techniques, a select logic block generates an SEL pulse to briefly open an aperture for reference injection. A necessary attribute of the SEL pulse is that it is sufficiently sharp and well-positioned to select the next reference edge. However, at high frequencies, the position of the SEL pulse impacts the delay of the MUX and hence introduces pattern jitter and spurs. This paper minimizes the spur by introducing a calibrated phase delay to properly position the SEL pulse with respect to the reference edge, and by minimizing the inherent error of the charge pump.