An 8mW 50MS/s CT ΔΣ modulator with 81dB SFDR and digital background DAC linearization

Author

Kauffman, John G. ; Witte, Pascal ; Becker, Joachim ; Ortmanns, Maurits

Author_Institution

Ulm Univ., Ulm, Germany

fYear

2011

fDate

20-24 Feb. 2011

Firstpage

472

Lastpage

474

Abstract

The intention of this work is to realize a power and area-efficient 50MS/S ΔΣ modulator with an OSR of only 10, an effective linearization without DEM, and a very low power ELD compensation. This is achieved by using a digital DAC error estimation and correction, and a compensation for finite gain-bandwidth (FGBW) in all feedback amplifiers. A multi-bit 3^rd-order, mixed feedforward-feedback compensation is used, which avoids the second DAC, limiting the swing of the first opamp, while reducing the STF peaking compared to an all feedforward topology.

Keywords

delta-sigma modulation; error compensation; feedback amplifiers; operational amplifiers; ΔΣ modulator; FGBW; OSR; SFDR; STF peaking; digital DAC error correction; digital DAC error estimation; digital background DAC linearization; feedback amplifier; finite gain-bandwidth; low power ELD compensation; mixed feedforward-feedback compensation; opamp; Bandwidth; Computer architecture; Delay; Distortion measurement; Estimation; Microprocessors; Modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-61284-303-2

Type

conf

DOI

10.1109/ISSCC.2011.5746402

Filename

5746402