A third-order DT ΔΣ modulator using noise-shaped bidirectional single-slope quantizer

In this paper, a prototype delta-sigma ADC is implemented in a 0.18μm 2P5M CMOS process. The input signal sampling capacitors are shared with the front-end DAC capacitors. The sampling frequency is 50MHz and oversampling ratio is 24. The out-of-band peaking is deliberately set to help the stability and to allow larger input signals to be processed by the loop. This modulator achieves 78.2dB peak SNDR and 79.3dB peak SNR while consuming 1.35mW analog and 1.55mW digital power from 1.5V supplies. The major portion of the digital power (1.3mW) is consumed by an overdesigned generic clock generator to provide flexibility in testing with various sampling frequencies. The rest of the digital power (0.25mW) includes the DLL, digital counter, DWA and the comparator. The achieved minimal analog power is the direct result of the extra order of noise shaping, and the elimination of the flash ADC and the typical large capacitive loading that comes with it. The FoM is 210fJ/conversion-step and it can easily be reduced further with redesign (i.e., eliminating the wasted clock generator power).