DocumentCode :
2896523
Title :
A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW
Author :
Perez, Aldo Pena ; Bonizzoni, Edoardo ; Maloberti, Franco
Author_Institution :
Univ. of Pavia, Pavia, Italy
fYear :
2011
fDate :
20-24 Feb. 2011
Firstpage :
478
Lastpage :
480
Abstract :
This third-order ΔΣ modulator, suitable for high-resolution low-power sensor systems, consumes 140μW to obtain 84dB SNDR with OSR=16 and 100kHz signal bandwidth. The achieved FoM is 54fJ/conversion-step. The DACs use a single resistive divider to generate 32 differential 5b reference voltages. The proposed scheme totally cancels the error caused by gradient in the resistance values. Resistor sizes and layout of the resistive DAC limit the high-order distortion terms and obtain an SFDR of 96dB at -4dBFS without the need for digital calibration or dynamic element matching (DEM).
Keywords :
delta-sigma modulation; low-power electronics; operational amplifiers; bandwidth 100 kHz; digital calibration; dynamic element matching; high-order distortion terms; high-resolution low-power sensor systems; low-power single op-amp third-order ΔΣ modulator; power 140 muW; resistance values; resistive DAC limit; resistor layout; resistor sizes; single resistive divider; word length 5 bit; Bandwidth; Calibration; Modulation; Noise; Power demand; Resistors; Semiconductor device measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-61284-303-2
Type :
conf
DOI :
10.1109/ISSCC.2011.5746405
Filename :
5746405
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2896523
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