A 4.8Gb/s impedance-matched bidirectional multi-drop transceiver for high-capacity memory interface

In this paper, first, we describe an impedance-matched bi-directional multi-drop (IMBM) DQ bus that can handle up to 4 slots, 8 drops at a data-rate of up to 4.8Gb/s. In the case of the SSTL DQ bus, the series resistor of Z0/2 can suppress ringing and attenuate reflections within the chan nel. But, the SSTL DQ bus is still not entirely free from reflections among the slots because the reflection coefficient of the SSTL DQ bus at the stub junctions is -1/4. However, the IMBM DQ bus that we propose makes the reflection coef ficient 0 as can be seen from the equations. Therefore, the IMBM DQ bus generates no reflection signal at each stub. Moreover, the IMBM DQ bus can send write signals of the same current level to every module according to its current division relation of lk and lk+1. The transceiver also receives the read signal from every module with the identical level, according to the reciprocity theorem. This characteristic produces identical transfer responses for all the modules regardless of their positions.