Title :
Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator
Author :
Gaedke, K. ; Borsum, M. ; Georgi, M. ; Kluger, A. ; Le Glanic, J.-P. ; Bernard, P.
Author_Institution :
Thomson Corporate Res., Hannover
Abstract :
The architecture and VLSI implementation of a programmable HD real-time motion estimator is presented. Due to the programmability, main video compression standards like MPEG-2, H.264, and VC-1 are supported. A sophisticated data flow concept in combination with a VLIW approach for controlling leads to a sustained utilization of the arithmetic resources of 95%. An area efficient architecture and design of the datapath consisting of 64 parallel processing elements reduced the required complexity to 1.2 million gates. With a first VLSI implementation in 90 nm standard cell semiconductor technology a maximum clock rate of 334 MHz was achieved. This design enables real-time motion estimation in HD format with 1920-1080 pixels at 25 Hz frame rate.
Keywords :
VLSI; data compression; integrated circuit design; logic design; motion estimation; programmable circuits; real-time systems; video coding; 25 Hz; 334 MHz; 90 nm; H.264; MPEG-2; VC-1; VLIW approach; VLSI implementation; data flow concept; parallel processing elements; programmable HD real-time motion estimator; standard cell semiconductor technology; video compression standards; Arithmetic; Hardware; High definition video; Motion estimation; Parallel processing; Prediction algorithms; Transform coding; VLIW; Very large scale integration; Video compression;
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
DOI :
10.1109/ISCAS.2007.378826
