An embedded DRAM technology for high-performance NAND flash memories

This paper demonstrates a prototype of embedded DRAM using a standard NAND flash memory process. This embedded DRAM can replace on-chip SRAM page buffers and other caches with minimum cost to enhance NAND flash memory performance. This opens up a new technical direction and wide applications for NAND flash memories. Figure 28.9.2(a) shows the concept of the embedded DRAM. An obstacle to embed DRAM in a NAND flash memory chip is a lack of cell charge, because the cell capacitance Cs using a planar MOS capacitor is limited to 3fF at the highest, whereas that of an ordinary embedded DRAM is around 20fF by using extra trenched or stacked capacitor process steps. However, even with a small 3fF cell, a cell node bias up to 4V, which is 4 times as high as the ordinary DRAM bias by taking advantage of the high-voltage NAND flash process, and a low parasitic capacitance bitline of 60fF, together enable sufficient ±100mV cell signals. A memory cell is composed of a cell transistor and a depletion-type MOS capacitor, and the cell size is 1.5μnf. The large 4V bias to the cell node is realized by adopting a self-boost technique, which is widely used for the program inhibit of NAND flash memory. After writing the bitline BL voltage of 2V V_int for "1" data and 0V for "0" data into a cell node and pulling down the wordline WL from 3.4V V_pp to 2V V_irιt, the plateline PL is boosted to 3.4V V_pp. Therefore, the cell node voltage of "1" data is self-boosted to around 4V due to cell transistor cut-off by negative V_gs-V_t, while that of "0" data is kept at ground due to cell transistor being turned-on.