EP2: 20–22nm technology options and design implications

The move to 22/20nm comes at the cost of an increased level of leakage and variability that both technology and product developers need to address. Lithography, still at 193nm, uses liquid immersion, double patterning, mask and source optimization, and increasingly-restrictive design rules. High-k Metal Gate methods, targeted to reducing gate leakage and Gate-Induced Drain Leakage (GIDL), have proponents of Gate-First (IBM, GLOBALFOUNDRIES) and Gate-Last (TSMC, Intel), also using different metals for p-channel and n-channel for Vt adjust ment. Partially-depleted SOI continues to be promoted by IBM and GLOBALFOUNDRIES. Under consideration for possible later introduc tion at 22/20nm are EUV, multi-beam E-beam and finfets. R&D dollars are increasing, once at 12% of revenue in 1998, now at 18% in 2010. As product design costs rise, the number of projects is declining, needing more synchronization of process and design development. Restrictive design rules (unidirectional poly, no jogs, dummy insertion, structured layout), adaptive architectures and expanded design for manufacturability are needed to address variability. Accurate layout aware modeling for local variability, well proximity effects, STI stress (LOD) and gate implementation are needed. Design enablement and technology-design col laboration are increasingly emphasized.