Micro-architectural optimization of a coarse-grained array based baseband processor

Software Defined Radios (SDR) has been introduced as the ultimate way to achieve the flexibility that is needed to cope with the many emerging wireless standards. A key challenge in the implementation of such radios for mobile terminals is meeting the performance and energy requirements. A suitable architecture template is the first requirement, but finding the optimal instance is as important. This paper shows that it is possible to half the power consumption of an already very energy efficient baseband processor by doing micro-architectural improvements. Overall a 2.6× improvement in energy efficiency and a 2.0× improvement in power consumption has been achieved, resulting in an average power consumption for the baseband processing of 108mW.