DocumentCode :
2896808
Title :
An optimization method of DMA transfer for a general purpose reconfigurable machine
Author :
Shida, Sayaka ; Shibata, Yuiochiro ; Oguri, Kiyoshi ; Buell, Duncan A.
Author_Institution :
Dept. of Comput. & Inf. Sci., Nagasaki Univ., Nagasaki
fYear :
2008
fDate :
8-10 Sept. 2008
Firstpage :
647
Lastpage :
650
Abstract :
DMA transfer between a CPU and an FPGA often becomes a bottleneck of current reconfigurable machines. The DMA transfer of the machines like SRC-6 supports streaming processing with on-board memory interleaving, but as a pre-processing of the interleaving, the CPU must reorder the data for applications with severe FPGA resource constraints. This paper empirically evaluates this overhead to reveal the trade-off point. The results show that a speedup is achieved by interleaved streaming DMA when 150 KB or lower data strings are transferred.
Keywords :
field programmable gate arrays; file organisation; logic design; microprocessor chips; CPU; DMA transfer; FPGA; general purpose reconfigurable machine; interleaved streaming; onboard memory interleaving; optimization method; resource constraints; streaming processing; Optimization methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2008. FPL 2008. International Conference on
Conference_Location :
Heidelberg
Print_ISBN :
978-1-4244-1960-9
Electronic_ISBN :
978-1-4244-1961-6
Type :
conf
DOI :
10.1109/FPL.2008.4630030
Filename :
4630030
Link To Document :
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