FPGA interconnect sizing using extended logical effort model

The proposed XLE model will enable us to calculate the delay of FPGA interconnect and determine closed form expressions for optimal transistor size, sensitivity and a minimal bound on delay. We will further extend it to cover process variations, resulting in a tool that can compare the statistical properties of different architectures. The models are simple and relatively technology independent and hence can be used to gain better intuition into the major causes of delay. Such a delay model can be used in optimization models and CAD tools as well as aid designers in developing new FPGA interconnect schemes.