Reconfigurable many-cores with lean interconnect

Two key research problems for emerging many-core architectures are the development of energy-efficient interconnects and, a tightly coupled issue, useful parallel programming models. The vast majority of current proposals advocates packed-switched networks on chip with dynamic routing. Such networks obviously benefit from well-known message passing techniques, but their complex switches, routers and buffers consume substantial amounts of energy. Moreover, some important classes of applications do not efficiently map to message passing schemes. The author has proposes a lean interconnect for many-cores following the principles of the reconfigurable mesh, a well-studied theoretical parallel programming model.