DocumentCode
2897148
Title
A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 μm CMOS
Author
Chen, Cheng ; Yuan, Jiren
Author_Institution
Dept. of Electroscience, Lund Univ.
fYear
2007
fDate
27-30 May 2007
Firstpage
1709
Lastpage
1712
Abstract
A 10-bit two-step subranging folding analog-to-digital converter (ADC) that converts signal at 500 MSample/s is presented. Using dual-channel preprocessing blocks with distributed sample-and-hold circuits and two-stage amplifiers in which auto-zero calibration technique is employed, the proposed 10-bit ADC has a wide input bandwidth (≫250MHz). The ADC consumes 124mW from a 1.2V power supply. The performance is verified by Spectre simulation in a digital 0.13μm CMOS process. The chip occupies an active area of 0.54mm2
Keywords
CMOS digital integrated circuits; amplifiers; analogue-digital conversion; sample and hold circuits; 0.13 micron; 10 bit; 124 mW; Spectre simulation; auto-zero calibration technique; digital CMOS process; distributed sample-and-hold circuits; dual-channel preprocessing blocks; subranging folding analog-to-digital converter; two-stage amplifiers; Bandwidth; CMOS technology; Calibration; Circuits; Clocks; Data preprocessing; Distributed amplifiers; Signal resolution; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.377923
Filename
4252987
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