A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor Interface

Author

Järvinen, Jere A M ; Saukoski, Mikko ; Halonen, Kari

Author_Institution

Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo

fYear

2007

fDate

27-30 May 2007

Firstpage

1713

Lastpage

1716

Abstract

This paper describes a ratio-independent algorithmic ADC architecture that is insensitive to capacitance ratio, amplifier offset voltage, amplifier input parasitics, and flicker noise. It requires only one differential amplifier, a dynamic latch, six capacitors, 36 switches, and some digital logic. The prototype 12-bit, 40 kS/s ADC with an active die area of 0.041 mm² is implemented in a 0.13 mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 68.4 muW power dissipation, the ADC achieves 80.2 dB SFDR and 63.3 dB SNDR.

Keywords

CMOS integrated circuits; analogue-digital conversion; capacitive sensors; differential amplifiers; flip-flops; operational amplifiers; 0.13 micron; 12 bit; 68.4 muW; CMOS integrated circuits; amplifier input parasitics; amplifier offset voltage; analog-to-digital converter; capacitive sensor interface; capacitors; differential amplifier; digital logic; dynamic latch; dynamically biased operational amplifier; flicker noise; ratio-independent algorithmic ADC; 1f noise; CMOS logic circuits; Capacitive sensors; Capacitors; Differential amplifiers; Parasitic capacitance; Power dissipation; Prototypes; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.377924

Filename

4252988