DocumentCode :
2897374
Title :
Accelerating adaptive background subtraction with GPU and CBEA architecture
Author :
Poremba, Matthew ; Xie, Yuan ; Wolf, Marilyn
Author_Institution :
Pennsylvania State Univ., University Park, PA, USA
fYear :
2010
fDate :
6-8 Oct. 2010
Firstpage :
305
Lastpage :
310
Abstract :
Background subtraction is an important problem in computer vision and is a fundamental task for many applications. In the past, background subtraction has been limited by the amount of computing power available. The task was performed on small frames and, in the case of adaptive algorithms, with relatively small models to achieve real-time performance. With the introduction of multi- and many-core chip-multiprocessors (CMP), more computing resources are available to handle this important task. The advent of specialized CMP, such as NVIDIA´s Compute Unified Device Architecture (CUDA) and IBM´s Cell Broadband Engine Architecture (CBEA), provides new opportunities to accelerate real-time video applications. In this paper, we evaluate the acceleration of background subtraction with these two different chip-multiprocessor (CMP) architectures (CUDA and CBEA), such that larger image frames can be processed with more models while still achieving real-time performance. Our analysis results show impressive performance improvement over a baseline implementation that uses a multi-threaded dual-core CPU. Specifically, the CUDA implementation and CBEA implementation can achieve up to 17.82X and 2.77X improvement, respectively.
Keywords :
computer graphic equipment; computer vision; coprocessors; multi-threading; video signal processing; GPU; IBM cell broadband engine architecture; adaptive algorithms; adaptive background subtraction; compute unified device architecture; computer vision; multi-and-many-core chip-multiprocessors; multithreaded dual-core CPU; real-time video applications; Adaptation model; Computational modeling; Computer architecture; Graphics processing unit; Instruction sets; Microprocessors; Pixel;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems (SIPS), 2010 IEEE Workshop on
Conference_Location :
San Francisco, CA
ISSN :
1520-6130
Print_ISBN :
978-1-4244-8932-9
Electronic_ISBN :
1520-6130
Type :
conf
DOI :
10.1109/SIPS.2010.5624808
Filename :
5624808
Link To Document :
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