DocumentCode :
2897872
Title :
Reduced-complexity multi-interpolator algebraic soft-decision Reed-Solomon decoder
Author :
Zhang, Xinmiao ; Zhu, Jiangli
Author_Institution :
Case Western Reserve Univ., Cleveland, OH, USA
fYear :
2010
fDate :
6-8 Oct. 2010
Firstpage :
398
Lastpage :
403
Abstract :
Algebraic soft-decision decoding (ASD) of Reed-Solomon (RS) codes can achieve significant coding gain with polynomial complexity. Among ASD algorithms, the low-complexity Chase (LCC) algorithm can achieve better performance-complexity tradeoff. This algorithm tests 2η vectors, and larger η leads to higher coding gain. One major step of the LCC decoding is the interpolation, and its latency grows exponentially with η. To reduce the latency, multiple interpolators can be used to test the vectors in parallel. However, they lead to large area requirement. This paper proposes to interpolate over the points in the test vectors in a different order. By making use of the properties of the interpolation points in the rearranged order, novel schemes are developed to simplify and share computations among the interpolators. From complexity analysis, the proposed interpolation scheme can achieve higher speed and reduce the area requirement by 30% for a (255, 239) RS code with η = 5 when 4-parallel interpolation is employed. The proposed interpolation architecture is incorporated into the LCC decoder and further optimizations are carried out. For the same RS code, the proposed decoder can achieve 16% speedup with 11% less area than the previous design.
Keywords :
Reed-Solomon codes; algebraic codes; communication complexity; decoding; interpolation; optimisation; polynomials; ASD algorithm; LCC decoder; LCC decoding; RS code; Reed-Solomon code; algebraic soft-decision decoding; coding gain; interpolation architecture; low-complexity chase algorithm; optimization; polynomial complexity; reduced-complexity multiinterpolator; Clocks; Computer architecture; Decoding; Hardware; Interpolation; Polynomials; Variable speed drives; Algebraic soft-decision decoding; Interpolation; Low-complexity Chase; Reed-Solomon codes; VLSI design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems (SIPS), 2010 IEEE Workshop on
Conference_Location :
San Francisco, CA
ISSN :
1520-6130
Print_ISBN :
978-1-4244-8932-9
Electronic_ISBN :
1520-6130
Type :
conf
DOI :
10.1109/SIPS.2010.5624880
Filename :
5624880
Link To Document :
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