DocumentCode

2898269

Title

Two approaches to charge control in saturated logic gates

Author

Hirsch, Laurence ; Moore, James ; Pollock, Lori ; Kons, J.

Author_Institution

Westinghouse Electric Corp,. Elkridge, MD, USA

Volume

IX

fYear

1966

fDate

9-11 Feb. 1966

Firstpage

14

Lastpage

15

Keywords

Delay; Diodes; Doping; Gettering; Gold; Logic circuits; Logic gates; Noise figure; Noise reduction; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference. Digest of Technical Papers. 1966 IEEE International

Conference_Location

Philadelphia, PA, USA

Type

conf

DOI

10.1109/ISSCC.1966.1157673

Filename

1157673