Title :
Design of logic-compatible embedded DRAM using gain memory cell
Author :
Weijie Cheng ; Jeong-Wook Cho ; Yeonbae Chung
Author_Institution :
Sch. of Electron. Eng., Kyungpook Nat. Univ., Daegu, South Korea
Abstract :
In this work, we present an embedded DRAM utilizing logic-compatible 2T gain cell. The memory cells are composed of a high-VTH write NMOS and a standard read NMOS. Due to the combination of low off-leakage write device and high mobility read device, this NMOS-based hybrid gain cell provides much improved data retention and read performance. At 1.2 V and 85 °C, the proposed bit-cell achieves 1.1× longer standby retention and 4.4× longer write disturbance retention compared to the PMOS-only 2T cell. The memory arrays operate with a logic-compatible supply voltage; /CS controlled 128-row refresh; and nondestructive read with speed comparable to 6T SRAM but 65 % smaller cell area. Design results from a test chip in a 130 nm logic CMOS technology exhibit the effectiveness of the proposed embedded memory techniques.
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; SRAM chips; embedded systems; logic design; NMOS-based hybrid gain cell; PMOS-only cell; SRAM; data retention; embedded memory techniques; gain memory cell; high mobility read device; high-VTH write NMOS; logic CMOS technology; logic-compatible embedded DRAM design; logic-compatible gain cell; logic-compatible supply voltage; low off-leakage write device; memory arrays; nondestructive read; read performance; size 130 nm; standard read NMOS; standby retention; temperature 85 C; voltage 1.2 V; write disturbance retention; CMOS integrated circuits; Decoding; Logic gates; Random access memory; Subthreshold current; Transistors; Very large scale integration; data retention; embedded DRAM; gain cell memory;
Conference_Titel :
SoC Design Conference (ISOCC), 2012 International
Conference_Location :
Jeju Island
Print_ISBN :
978-1-4673-2989-7
Electronic_ISBN :
978-1-4673-2988-0
DOI :
10.1109/ISOCC.2012.6407073