Task mapping techniques for embedded many-core SoCs

Author

Kaida, Junya ; Hieda, Tomohiro ; Taniguchi, Ittetsu ; Tomiyama, Hiroyuki ; Hara-Azumi, Y. ; Inoue, Ken

Author_Institution

Dept. of Electron. & Comput. Eng., Ritsumeikan Univ., Kusatsu, Japan

fYear

2012

fDate

4-7 Nov. 2012

Firstpage

204

Lastpage

207

Abstract

This paper proposes static task mapping techniques for embedded many-core SoCs. The proposed techniques take into account both task and data parallelisms of the tasks in order to efficiently utilize the potential parallelism of the many-core architecture. Two approaches are proposed for static mapping: one approach is based on integer linear programming and the other is based on a greedy algorithm. In addition, a static mapping technique considering dynamic task switching is proposed. Experimental results show the effectiveness of the proposed techniques.

Keywords

embedded systems; greedy algorithms; integer programming; linear programming; multiprocessing systems; parallel processing; system-on-chip; task analysis; data parallelisms; dynamic task switching; embedded many-core SoC; embedded system-on-chip; greedy algorithm; integer linear programming; potential parallelism; static task mapping techniques; Greedy algorithms; Multicore processing; Parallel processing; Runtime; Switches; System-on-a-chip; Tiles; embedded systems; many-core SoCs; system-level design; task mapping;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2012 International

Conference_Location

Jeju Island

Print_ISBN

978-1-4673-2989-7

Electronic_ISBN

978-1-4673-2988-0

Type

conf

DOI

10.1109/ISOCC.2012.6407075

Filename

6407075