Parallel and digit-serial implementations of area-efficient 3-Operand Decimal Adders

In this paper, parallel and digit-serial implementations of area-efficient 3-operand decimal adders are proposed. By using proposed analyzer circuits and the generation of correction terms with recursive schemes, our proposed decimal adders could perform efficient additions with three operands. Unit gate estimates and synthesis results show that our proposed adders are more area-efficient than those previously proposed decimal adders with three operands under the same delay constraints. Also the power consumptions for our decimal adders are lesser. In addition to parallel implementations, the digit-serial 3-operand adders are easily developed to increase the throughput and the operating frequency due to area efficiency. Our proposed decimal adders could be applied to ease the tremendous computation efforts for decimal computations such as multi-operand decimal additions, decimal multiplications and divisions.