DocumentCode :
2898778
Title :
Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building
Author :
Wang, Yanfeng ; Zhou, Qiang ; Hong, Xianlong ; Cai, Yici
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing
fYear :
2007
fDate :
27-30 May 2007
Firstpage :
2040
Lastpage :
2043
Abstract :
Minimization of clock network is traditionally achieved by clock routing, which may be helpless for a poor placement result. In this paper, a novel dynamic clock-tree building technique integrated into placement for zero-skew design is proposed. This method combines a pre-designed clock-tree with the force-directed placement procedure to navigate the register placement for minimizing the clock network. Meanwhile, a new model of multi-level bounding box and technique of multi-level attractive force are proposed to give a better local distribution of registers. Experiments on several standard-cell benchmarks indicate an average 26.1% clock network reduction with the logic cell placement preserved well.
Keywords :
clocks; integrated circuit layout; clock routing; clock-tree aware placement; dynamic clock-tree building technique; force-directed placement procedure; logic cell placement; multilevel attractive force; multilevel bounding box; register placement; zero-skew design; Buildings; Clocks; Computer science; Frequency; Geometry; Logic; Navigation; Power dissipation; Routing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location :
New Orleans, LA
Print_ISBN :
1-4244-0920-9
Electronic_ISBN :
1-4244-0921-7
Type :
conf
DOI :
10.1109/ISCAS.2007.378498
Filename :
4253069
Link To Document :
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