Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building

Minimization of clock network is traditionally achieved by clock routing, which may be helpless for a poor placement result. In this paper, a novel dynamic clock-tree building technique integrated into placement for zero-skew design is proposed. This method combines a pre-designed clock-tree with the force-directed placement procedure to navigate the register placement for minimizing the clock network. Meanwhile, a new model of multi-level bounding box and technique of multi-level attractive force are proposed to give a better local distribution of registers. Experiments on several standard-cell benchmarks indicate an average 26.1% clock network reduction with the logic cell placement preserved well.