DocumentCode :
2898830
Title :
Partial-LastZ: An optimized hybridization technique for 3D NoC architecture enabling adaptive inter-layer communication
Author :
Rahmani, Amine ; Liljeberg, Pasi ; Plosila, Juha ; Ka Lok Man ; Youngmin Kim ; Tenhunen, Hannu
Author_Institution :
Dept. of IT, Univ. of Turku, Turku, Finland
fYear :
2012
fDate :
4-7 Nov. 2012
Firstpage :
281
Lastpage :
284
Abstract :
Three-dimensional (3D) integration offers greater device integration, reduced signal delay and reduced interconnect power. It also provides greater design flexibility by allowing heterogeneous integration. Stacked mesh 3D NoC architecture was proposed to take advantage of the intrinsic capability of reducing the wire length in 3D ICs. However, this architecture still exacerbates the on-chip power density and router cost. In this paper, we propose a novel hybridization scheme for inter-layer communication using efficient 5-input routers to enhance the overall system power, performance, and area characteristics of the existing Hybrid NoC-Bus 3D mesh architecture. By defining a rule for routing algorithms called LastZ, the proposed area-efficient architecture decreases the overall average hop count of a NoC-based system compared to the existing architectures. We further improve this design by proposing partial-LastZ-based 3D NoC-bus hybrid architecture to provide adaptivity for implementing congestion-aware and fault-tolerant inter-layer routing algorithms. Extensive quantitative experiments demonstrate up to 16% performance improvement compared to the full LastZ-based 3D NoC-bus hybrid architecture and around 20% area reduction compared to the typical hybrid NoC-Bus 3D mesh architecture.
Keywords :
fault tolerance; integrated circuit interconnections; network routing; network-on-chip; optimisation; 3D IC; 5-input routers; adaptive interlayer communication; congestion-aware interlayer routing algorithms; device integration; fault-tolerant interlayer routing algorithms; on-chip power density; optimized hybridization technique; partial-LastZ-based 3D mesh NoC-bus hybrid architecture; reduced interconnect; reduced signal delay; router cost; stacked mesh 3D NoC architecture; three-dimensional integration; Algorithm design and analysis; Computer architecture; Educational institutions; Power demand; Routing; System-on-a-chip; 3D ICs; 3D Networks-on-Chip; NoC-Bus Hybridization; Routing Algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SoC Design Conference (ISOCC), 2012 International
Conference_Location :
Jeju Island
Print_ISBN :
978-1-4673-2989-7
Electronic_ISBN :
978-1-4673-2988-0
Type :
conf
DOI :
10.1109/ISOCC.2012.6407095
Filename :
6407095
Link To Document :
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