An efficient dual-supply design for low-power mobile systems

This paper overviews dual-supply design for low-power mobile systems in deep sub-micron technology. Various dual-supply design schemes were investigated for real world design in terms of power efficiency. The analysis showed that a dual-supply design applied to a clock network was more efficient than that applied to data-path logics. For example, the dual-supply clock network with clock-gating level converter can minimize the penalties of level conversion in terms of power, area, and performance. It can also achieve higher operating frequency due to the mitigated timing constraint on gated clocks. Frequency doubling readily derived from existing level converters can save more power by halving the clock frequency. Furthermore, the clock-gating level converter can enable a system to exploit pulse-based flip-flops without pulse generators, resulting in more power reduction.