A new latch-up test structure for practical design methodology for internal circuits in the standard cell-based CMOS/BiCMOS LSIs

A latch-up test structure is proposed as a practical design methodology for high-density internal circuits in standard cell-based CMOS/BiCMOS LSIs. Both locally injected trigger current and uniformly generated trigger current can be measured with this test structure. Focusing on the difference in the well shunt resistance between local and uniform trigger currents, a practical guideline at uniformly generated trigger current in the well is presented for the periodic placement of well contacts dependent on parasitic device parameters, on generated trigger current level, and on layout pattern size