Title :
A novel test structure for monitoring technological mismatches in DRAM processes
Author :
Geib, H. ; Weber, W. ; Wohlrab, E. ; Risch, L.
Author_Institution :
Siemens AG, Munich, Germany
Abstract :
Based on a typical 1 6-Mb dynamic-RAM (DRAM) sense amplifier using 0.6-μm design rules, a test structure was designed and the minimum signal voltage for reliable operation of the sense amplifier was determined. The analysis of the measured data provides a monitor for DRAM process control. Variations in gate lengths and capacitances and the influence of the decoupling transistors located between bitlines and sense amplifier were investigated. The local variation in threshold voltage was investigated on a separate test structure on the same wafer. In this way the contribution to the minimum sense signal attributed to mismatches in current gain and parasitic transistor capacitances can be separated. The minimum storage cell capacitance for which correct sensing was possible was determined
Keywords :
DRAM chips; capacitance; integrated circuit testing; 0.6 micron; 16 Mbit; DRAM processes; bitlines; current gain; decoupling transistors; gate lengths; minimum signal voltage; parasitic transistor capacitances; sense amplifier; storage cell capacitance; technological mismatches; test structure; threshold voltage; Capacitance; Circuits; Latches; MOSFETs; Monitoring; Operational amplifiers; Random access memory; Signal design; Testing; Threshold voltage;
Conference_Titel :
Microelectronic Test Structures, 1992. ICMTS 1992. Proceedings of the 1992 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0535-3
DOI :
10.1109/ICMTS.1992.185929
