Title :
C45 ultra low k wafer technology with Cu wire bonding
Author :
Leng, Eu Poh ; Siong, Chin Teik ; Seong, Lee Boon ; Leong, Philip ; Gunasekaran ; Song, James ; Mock, K.S. ; Siew, C.W. ; Sivakumar ; Kid, Wong Boh ; Weily, Chew
Author_Institution :
Freescale Semicond. (M) Sdn. Bhd., Petaling Jaya, Malaysia
fDate :
Nov. 30 2010-Dec. 2 2010
Abstract :
As gold price continues to move in an overall rising trend, conversion to Cu wire has been given great focus as the main effort for cost reduction. Cu is a good alternative due to 26% lower electrical resistivity than Au, hence much higher electrical conductivity. However, Cu free-air-ball and bonded ball hardness are 34% and 60% higher than that of Au, hence increases the stress on bond pad and chip. Although Cu wire price is generally only 5 to 10% of Au wire cost depending on wire diameter, but bonding with a much harder material like Cu requires great characterization effort due to the a much higher level of unknowns and complexities, especially when dealing with ultra fine pitch and ultra low k wafer technology.
Keywords :
ball grid arrays; copper; lead bonding; palladium; wafer bonding; wafer level packaging; BGA; Cu; DOE process; FAB oxidation; Pd; bond pad peeling; bond peel strength; bonded ball hardness; bonding parameters optimization; capillary selection; copper free-air-ball hardness; copper wire bonding; electrical conductivity; electrical resistivity; semiconductor industry; temperature 175 C; thermal aging testing; time 168 hour; wafer technology; wire selection process; Copper; Gold; Robustness; Substrates; US Department of Energy; Wire;
Conference_Titel :
Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International
Conference_Location :
Melaka
Print_ISBN :
978-1-4244-8825-4
DOI :
10.1109/IEMT.2010.5746739