DocumentCode
2899313
Title
Evolutionary development of Wafer Level Packaging
Author
Hunt, John
Author_Institution
ASE (US) Inc., Tempe, AZ, USA
fYear
2010
fDate
Nov. 30 2010-Dec. 2 2010
Firstpage
1
Lastpage
2
Abstract
IBM created the wafer processing technology and concepts more than 45 years ago that would later enable what we call Wafer Level Packaging. With its introduction of the Controlled Collapse Chip Connect (C4) solder bumping process for use in its Solid Logic Technology package, it paved the way for the larger solder bump technology that enabled die to be mounted directly on circuit boards using standard surface mount equipment, and standard pitch circuit board technologies. Over ten years ago, Wafer Level Chip Scale Packaging (WLCSP) came into volume production, with all of the “packaging” done while still in wafer form. It began slowly, with very small packages having solderball counts of 2-6 I/Os. Over the years, the production volumes have grown, and so has the I/O count. Much of the industry still perceives WLCSPs as limited to low I/O count simple applications. However, within the last few years, there have been growing demands for WLCSP packages with I/O counts of 300 and greater, and with higher levels of complexity.
Keywords
soldering; surface mount technology; wafer level packaging; C4 solder bumping; IBM; controlled collapse chip connect solder bumping; evolutionary development; solid logic technology package; surface mount equipment; wafer level packaging; wafer processing technology; Assembly; Electronic components; Packaging; Production; Three dimensional displays; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International
Conference_Location
Melaka
ISSN
1089-8190
Print_ISBN
978-1-4244-8825-4
Type
conf
DOI
10.1109/IEMT.2010.5746740
Filename
5746740
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