Yield test structures and their use for process development

Describes yield test structure design and test methodology for high-density bipolar integrated circuits. The test structure design makes it possible not only to unlayer failure modes electronically for process development, but also to reassemble them for yield projection. The methodology of critical area computation and simulation that serves as the bridging between test structures and product is described. It is shown how test structures can be used to establish or adjust process windows for emitter to collector leakage, and emitter and collector contacts