Title :
Yield test structures and their use for process development
Author_Institution :
IBM Corp., Hopewell Junction, NY, USA
Abstract :
Describes yield test structure design and test methodology for high-density bipolar integrated circuits. The test structure design makes it possible not only to unlayer failure modes electronically for process development, but also to reassemble them for yield projection. The methodology of critical area computation and simulation that serves as the bridging between test structures and product is described. It is shown how test structures can be used to establish or adjust process windows for emitter to collector leakage, and emitter and collector contacts
Keywords :
bipolar integrated circuits; failure analysis; integrated circuit testing; large scale integration; production testing; collector contacts; critical area computation; emitter contacts; emitter to collector leakage; failure modes; high-density bipolar integrated circuits; process development; process windows; test methodology; yield projection; yield test structure design; Assembly; Circuit testing; Condition monitoring; Design methodology; Inspection; Integrated circuit technology; Integrated circuit testing; Integrated circuit yield; Manufacturing; Optical microscopy;
Conference_Titel :
Microelectronic Test Structures, 1992. ICMTS 1992. Proceedings of the 1992 International Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0535-3
DOI :
10.1109/ICMTS.1992.185935
