Title :
The challenges of high density wires in C45SOI 40µm package
Author :
Yew, Low Boon ; Teck, Siong Chin
Author_Institution :
Freescale Semicond. Malaysia Sdn. Bhd., Selangor, Malaysia
fDate :
Nov. 30 2010-Dec. 2 2010
Abstract :
For wirebonded IC package, the industry has moved from conventional ~70um die pad pitch to ~40um pad pitch for better device and cost performance. In addition to the finer pitch challenge, thinner wires have also been introduced. These process advances have led to wire shorting and wire sweep being critical in package reliability and production yield. In this study, a DOE was designed to evaluate various factors such as wire diameter, wire length, wire gaps and layout, and mold transfer speed effect on wire sweep. The test vehicle used is a 31×31mm2 Thermally Enhanced PBGA version II (TePBGA II). The main response monitored was wire sweep %. As it turned out. the results compiled showed that wire diameter is the dominant factor affecting wire sweep.. In order to continue to be able to use the thinner wires, the other secondary factors such as the wire length need to be reduced and wire layout to be optimized. The main portion of this paper describes the evaluation accomplished in minimizing wire sweep while allowing the use of thinner wires.
Keywords :
ball grid arrays; design of experiments; integrated circuit interconnections; integrated circuit layout; integrated circuit packaging; integrated circuit reliability; lead bonding; C45SOI package; DOE; TePBGA II; Thermally Enhanced PBGA version II; high density wire; mold transfer speed effect; package reliability; pad pitch; production yield; size 40 mum; wire diameter; wire gaps; wire layout; wire length; wirebonded IC package; Current measurement; Heating; Layout; Lead; Logic gates; US Department of Energy;
Conference_Titel :
Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International
Conference_Location :
Melaka
Print_ISBN :
978-1-4244-8825-4
DOI :
10.1109/IEMT.2010.5746743