Dual Active-Capacitive-Feedback Compensation for Area-Efficient Three-Stage Amplifiers

Author

Guo, Song ; Lee, Hoi

Author_Institution

Dept. of Electr. Eng., Dallas Univ., Richardson, TX

fYear

2007

fDate

27-30 May 2007

Firstpage

2188

Lastpage

2191

Abstract

This paper presents a dual active-capacitive-feedback compensation (DACFC) scheme for a three-stage amplifier in large capacitive-load applications. The proposed DACFC is first reported scheme, which can generate two left-half-plane zeros to compensate for the negative phase shift due to the amplifier non-dominant complex poles. The value of compensation capacitors can thus be significantly reduced to widen the gain-bandwidth product and decrease the chip area while maintaining the stability of the amplifier. Implemented in a standard 0.35mum CMOS process, the proposed amplifier only requires the total compensation capacitance of 4.3pF to achieve the gain-bandwidth product of 5.2MHz and the phase margin of 61deg when driving a 500pF//25kOmega load. The amplifier dissipates 330muW power under a 2V input supply.

Keywords

CMOS analogue integrated circuits; compensation; feedback amplifiers; poles and zeros; 0.35 micron; 2 V; 330 muW; 4.3 pF; 5.2 MHz; CMOS process; amplifier nondominant complex poles; compensation capacitors; dual active-capacitive-feedback compensation; gain-bandwidth product; left-half-plane zeros; negative phase shift; three-stage amplifiers; Bandwidth; CMOS process; Capacitors; Frequency; Operational amplifiers; Parasitic capacitance; Poles and zeros; Power amplifiers; Power integrated circuits; Stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on

Conference_Location

New Orleans, LA

Print_ISBN

1-4244-0920-9

Electronic_ISBN

1-4244-0921-7

Type

conf

DOI

10.1109/ISCAS.2007.378608

Filename

4253106