Dependence of SPICE Level 3 model parameters with transistor size

Author

Perelló, C. ; Lozano, M. ; Cané, C. ; LoraTamayo, E.

Author_Institution

Centre Nacional de Microelectron., Univ. Au,tonoma de Barcelona, Spain

fYear

1992

fDate

16-19 Mar 1992

Firstpage

84

Lastpage

89

Abstract

An automated sequential parameter extraction procedure was applied to different MOS device sizes, for the SPICE Level 3 model, to investigate the transistor size influence on the extracted parameters. The extractor was fast enough to be used directly on wafer mapping. The results of its use on different size devices are presented. The parameters extracted on 21 groups of NMOS transistors with varying sizes are presented. The curves show that there are important variations, and an accurate fit can only be achieved if the parameters used are a function of device size

Keywords

SPICE; insulated gate field effect transistors; semiconductor device models; MOS device sizes; NMOS transistors; SPICE Level 3 model parameters; automated sequential parameter extraction; transistor size; wafer mapping; Analog circuits; Circuit simulation; Data mining; Digital circuits; Intrusion detection; MOS devices; MOSFETs; Optimization methods; SPICE; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1992. ICMTS 1992. Proceedings of the 1992 International Conference on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0535-3

Type

conf

DOI

10.1109/ICMTS.1992.185943

Filename

185943