Miniaturization innovation evolution of electronics packaging - what´s coming next…?

Intel´s Moore´s Law focuses on shrinking the transistors in the silicon to be able to pack more and more transistors for a given area. In general, Intel has been able to double the transistor count every 18-24 months and has been doing so while keeping the silicon size at about the same size or even smaller. The key implication to that trend has been the I/O density that needs to be routed through the packaging is also increasing (ie. More I/O count per area). This sharing will explain the evolution of Intel packaging technologies to support the increased density and complexity in the silicon design. It highlights the challenges and trends of flip chip assembly packaging technology based on the needs to meet Moore´s Law. It will also cover the challenges to meet the yield, manufacturability and reliability requirements while keeping the overall packaging cost at an affordable level. For this attempt, the presentation will discuss topics such as fine line spacing and fine C4 bump pitch for high density substrate, robust lead-free interconnect solder system and the surface finish associated with the metallurgy for both the C4 and the board-level interconnects. Towards the end, the needs of the emerging high density system-on-chip (SOC) and package-on-package (POP) technologies used for the hand-held & mobile internet devices will also be covered. This exciting technology trend drives for lower cost, higher performance and smaller form factor. To meet that needs, it will require significant innovation in research and development for future microelectronic packaging.