DocumentCode
2899565
Title
Miller Compensation: Optimization with Current Buffer/Amplifier
Author
Aloisi, Walter ; Di Cataldo, Giuseppe ; Palumbo, Gaetano ; Pennisi, Salvatore
Author_Institution
Dipt. di Ingegneria Elettrica Elettronica e dei Sistemi, Univ. di Catania
fYear
2007
fDate
27-30 May 2007
Firstpage
2216
Lastpage
2219
Abstract
A novel design-oriented approach for Miller compensation exploiting current buffer/amplifiers is described. The analysis enables a simple design procedure to be outlined, which is in turn applied to a two-stage CMOS OTA driving a large capacitive load. Assuming a 100-pF load, three example compensation networks were designed using alternatively a compensation capacitor as low as 1.3 pF, 0.6 pF and 250 fF. Simulations in very good agreement with theoretical results are also given.
Keywords
CMOS analogue integrated circuits; buffer circuits; current mirrors; operational amplifiers; Miller compensation; compensation capacitor; current amplifier; current buffer; two-stage CMOS OTA; Bandwidth; Capacitance; Capacitors; Design optimization; Feedback loop; Frequency; Performance analysis; Stability; Transconductance; Transfer functions;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on
Conference_Location
New Orleans, LA
Print_ISBN
1-4244-0920-9
Electronic_ISBN
1-4244-0921-7
Type
conf
DOI
10.1109/ISCAS.2007.378722
Filename
4253113
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