The use of a digital multiplexer to reduce process control chip pad count

A method for more area efficient accessing of digital test structures is reported. It was demonstrated that, for a given number of pads, the diode interconnect scheme, which places a diode in series with each test element to suppress alternate current paths, enables a larger number of test elements to be accessed than would be possible with more conventional methods. Further pad economy was demonstrated by the use of digitally addressed multiplexers which allow on-chip switching of the force and sense instruments to test elements incorporated in the diode interconnect scheme