A modular 0.7 μm CMOS JESSI test chip for multi purpose applications

Author

Brenner, Thomas ; Maene, Nova ; Lindenkreuz, Steffi ; Le Ber, Jacques ; Richter, H. ; Janssens, Edmond ; Morin, Gérard ; Hänseler, Josef

Author_Institution

Alcatel Sel, Stuttgart, Germany

fYear

1992

fDate

16-19 Mar 1992

Firstpage

160

Lastpage

165

Abstract

A CMOS 0.7-μm test chip for technology and model parameter measurements and reliability testing is presented. The basic concept is based on well-defined standardized modules with fixed sizes. It was designed by eight European companies with common JESSI (Joint European Submicron Silicon) design rules. The focus was on high-frequency test structures and connections for highly accurate on-wafer measurements and deembedding methods over a wide frequency range

Keywords

CMOS integrated circuits; circuit reliability; integrated circuit testing; modules; 0.7 micron; CMOS JESSI test chip; Joint European Submicron Silicon; deembedding methods; high-frequency test structures; model parameter measurements; on-wafer measurements; reliability testing; standardized modules; Battery powered vehicles; CMOS technology; Chip scale packaging; Circuit testing; Data mining; Frequency measurement; Measurement standards; Probes; Semiconductor device measurement; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1992. ICMTS 1992. Proceedings of the 1992 International Conference on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0535-3

Type

conf

DOI

10.1109/ICMTS.1992.185960

Filename

185960