• DocumentCode
    2899781
  • Title

    Current technology barriers and future direction for packaging

  • Author

    Tsukada, Yutaka

  • Author_Institution
    i-PACKS, Ritsumeikan Univ., Kusatsu, Japan
  • fYear
    2010
  • fDate
    Nov. 30 2010-Dec. 2 2010
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    Two decades have passed since the introduction of packaging technology with underfill reinforced flip chip bonding and organic chip carrier. The high performance and low cost packaging technology has been facing serious barriers for moving to the next generation. What should be the ranges of joint and wiring ground rules to shoot for the next step? What are the issues for moving to the step and does any solution exists for each issues? How to resolve the barrier for the cost? What is the area to contribute to the environmental issues after Pb free solder? Current status of such questions and direction for the future will be discussed.
  • Keywords
    electronics packaging; flip-chip devices; solders; current technology barrier; free solder; organic chip carrier; packaging technology; underfill reinforced flip chip bonding; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Manufacturing Technology Symposium (IEMT), 2010 34th IEEE/CPMT International
  • Conference_Location
    Melaka
  • ISSN
    1089-8190
  • Print_ISBN
    978-1-4244-8825-4
  • Type

    conf

  • DOI
    10.1109/IEMT.2010.5746763
  • Filename
    5746763