VLSI interconnect linewidth variation: a method to characterize depth of focus and proximity effects

Describes two types of test structure that are used to characterize a VLSI process. The first is a depth-of-focus structure to measure the linewidth with differing amounts of underlying topography. The second is a proximity test structure. Scaling of VLSI ICs is increasing the number of levels of interconnections and decreasing the wiring pitches. Variations in metal linewidth can directly affect the delay and power dissipation. The effect of the underlying layers on the metal width was analyzed by using the test structures. The effect of the underlying levels was shown to increase the metal line resistance by 15% and to increase the standard deviation by 140% for a triple-level metal. The experimental data were analyzed by using the SAMPLE program