Abstract :
Moore´s law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC/Si integration, which is a very complicate subject. It involves component and system designs, FAB, packaging assembly and testing, material suppliers, and equipment suppliers. The key enabling technologies for 3D IC integration are, e.g., electrical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip strength measurement and improving, lead-free microbump forming and assembly, low temperature C2W and W2W bonding, and thermal management. In this course, all these enabling technologies (except electrical) will be discussed. Most of the materials are based on the technical papers published within the past 3 years by others and the instructor.
Keywords :
integrated circuit design; lithography; system-in-package; system-on-chip; thermal management (packaging); three-dimensional integrated circuits; wafer level packaging; 3D IC integration; 3D IC-Si integrations; FAB; Moore´s law; WLP; electrical design; known good die; lead-free microbump forming; lithography integration; lithography scaling; mechanical design; microelectronic industry; packaging assembling; packaging testing; system design; system-in-package; system-on-chip; thermal design; thermal management; thin chip strength measurement; through silicon via filling; through silicon via forming; wafer handling; wafer thinning; Assembly; Bonding; Integrated circuits; Lead; Micromechanical devices; Packaging; Three dimensional displays;
