Title :
Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)
fDate :
April 27 1997-May 1 1997
Abstract :
The following topics were covered: core and processor test; RAM test; BIST; current testing techniques; delay test and diagnosis; fault modeling and parametric test; verification and debugging; analog test; sequential circuits test; concurrent checking; test of regular structures; fault simulation and redundancy identification; mixed signal test; on-line testing and fault-tolerant design; scan and boundary scan; testability analysis, thermal and elevated testing
Keywords :
VLSI; automatic testing; boundary scan testing; built-in self test; computer testing; fault diagnosis; integrated circuit testing; logic testing; BIST; RAM test; VLSI testing; analog test; boundary scan; concurrent checking; current testing techniques; debugging; delay diagnosis; delay test; elevated testing; fault modeling; fault simulation; fault-tolerant design; mixed signal test; online testing; parametric test; processor test; redundancy identification; sequential circuits test; thermal testing; verification;
Conference_Titel :
VLSI Test Symposium, 1997., 15th IEEE
Conference_Location :
Monterey, CA, USA
Print_ISBN :
0-8186-7810-0
DOI :
10.1109/VTEST.1997.599433
