Title :
Channel thermal noise and its scaling impact on deep sub-100nm MOSFETs
Author :
Tan, Ge ; Chen, Chih-Hung ; Hung, Bigchoug ; Lei, Peiming ; Yeh, Chune-Sin
Author_Institution :
Dept. of Electr. & Comput. Eng., McMaster Univ., Hamilton, ON, Canada
Abstract :
In this paper, we present the noise behavior of deep sub-100 nm bulk MOSFETs in 60 nm devices and predict that down to 17 nm. Analytical MOSFET channel thermal noise models are presented and calibrated using experimental data from 60 nm devices. Technology scaling issue on noise performance is also examined by applying the technology parameters presented in International Technology Roadmap for Semiconductors (ITRS) 2009 edition. Simulation results show that the noise improvement stops at around 29 nm technology node due to the increased gate resistance. Increasing the finger number is necessary to retain noise improvement in future technology nodes.
Keywords :
MOSFET; semiconductor device models; semiconductor device noise; channel thermal noise model; deep subnanometer bulk MOSFET; gate resistance; international technology roadmap for semiconductors; metal oxide semiconductor field effect transistor; scaling impact; size 60 nm; technology scaling issue; Fingers; Logic gates; MOSFETs; Noise; Noise measurement; Resistance; Thermal noise; Channel thermal noise; Gate resistance; MOSFET scaling; Noise modeling; Noise parameters;
Conference_Titel :
Noise and Fluctuations (ICNF), 2011 21st International Conference on
Conference_Location :
Toronto, ON
Print_ISBN :
978-1-4577-0189-4
DOI :
10.1109/ICNF.2011.5994342
