A 400 Mb/s clock and data recovery PLL system in a 0.5 μm CMOS ASIC process

Describes the design of a phase locked loop ( PLL) system for clock and data recovery ( CDR) on a 400Mb/s serial data stream; such systems are frequently required for retiming purposes within data communication applications. Within the transmission system, deterministic and random mechanisms cause temporal degradation of the pulse edges, often described as jitter, and CDR circuits are often employed to restore signal quality