DocumentCode :
2901049
Title :
Architectural considerations for certification of real-time multi-core systems
Author :
Huyck, P.
Author_Institution :
Green Hills Software, Palm Harbor, FL, USA
fYear :
2013
fDate :
5-10 Oct. 2013
Abstract :
To satisfy the increasing demands in computing throughput, new processor designs are frequently expanding their support for parallel operations, including multiple memory controllers, caches, and various I/O devices, but especially multiple processor cores. For developers of real-time embedded systems with security and/or safety-critical computing requirements, the advent of processors that include multiple cores has created a fundamental problem: how to satisfy certification considerations so that safety and/or security related applications can execute on real-time multi-core based partitioning enforcing systems. This paper examines some architectural considerations that may be taken into account as part of safety and/or security certification of a partitioning operating system that supports the scheduling of multiple applications on a multi-core processor. In particular, it covers a set of considerations and challenges associated with using multiple cores as part of an architecture that supports simultaneous execution of applications on different cores and as part of an architecture that supports simultaneous use of multiple cores cooperatively within an application. This includes high-level considerations of safety and security topics such as, shared resource management, caching, covert channels, and fault management. In addition, it examines the use of synchronous time-scheduling controls as a means to resolve some of the safety and security related issues. This paper, by examining and detailing some of the high-level safety and security considerations associated with multi-core processor architectures, is intended to demonstrate the benefits of utilizing synchronous time-scheduling controls across the entire multi-core processor as a means to resolve some of the issues. Developers of real-time embedded systems can maximize the benefit of multi-core processors through understanding the types of architectural features that may be necessary to resolve specific sa- ety and/or security issues.
Keywords :
certification; embedded systems; multiprocessing systems; operating systems (computers); processor scheduling; safety; security of data; I/O devices; caches; caching; covert channels; fault management; high-level safety; multicore processor architectures; multiple memory controllers; multiple processor cores; processor designs; real-time embedded systems; real-time multicore based partitioning enforcing systems; real-time multicore system ceritification; safety-critical computing; security certification; shared resource management; synchronous time-scheduling controls; Certification; Multicore processing; Process control; Robustness; Safety; Security; Software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Digital Avionics Systems Conference (DASC), 2013 IEEE/AIAA 32nd
Conference_Location :
East Syracuse, NY
ISSN :
2155-7195
Print_ISBN :
978-1-4799-1536-1
Type :
conf
DOI :
10.1109/DASC.2013.6712636
Filename :
6712636
Link To Document :
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