Assessing SRAM test coverage for sub-micron CMOS technologies

Author

Kim, Vonkyoung ; Chen, Tom

Author_Institution

Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA

fYear

1997

fDate

27 Apr-1 May 1997

Firstpage

24

Lastpage

30

Abstract

This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are evaluated based on their functional fault class coverages

Keywords

CMOS memory circuits; SRAM chips; fault diagnosis; integrated circuit testing; probability; 0.5 to 1 mum; SRAM test coverage assessment; coupling faults; data retention faults; functional fault class coverages; memory array; memory fault coverages; memory fault probability model; memory test algorithms; physical defects; stuck-at faults; stuck-open faults; submicron CMOS technologies; transition faults; CMOS process; CMOS technology; Data mining; Manufacturing; Predictive models; Probability distribution; Random access memory; SRAM chips; Semiconductor device modeling; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1997., 15th IEEE

Conference_Location

Monterey, CA

ISSN

1093-0167

Print_ISBN

0-8186-7810-0

Type

conf

DOI

10.1109/VTEST.1997.599437

Filename

599437