Sampling Clock Frequency Offset Compensation for Feature Detection in Spectrum Sensing

Reliable spectrum sensing is one of the main challenges in the development of cognitive radios. To achieve the high probability of detection at very low SNRs, some feature detection schemes have been proposed in the literature based on the cyclo-stationarity theorem. One limitation of such methods is their high sensitivity to RF and analog impairments. This paper focuses on analysis and compensation of sampling clock frequency offset (SCFO) between the DAC (at transmitter side) and the ADC (at detector side). We show that for an SCFO of 20 ppm and for a pilot-aided cyclo-stationary detector, the performance degradation in detection thresholds reach 7 dB and 12 dB for 50 ms and 100 ms sensing periods, respectively. We then present a method to compensate for such significant degradations in the presence of SCFO. Our analysis and simulations show that using this technique, we can achieve a performance within 1.5 dB of the no-offset ideal scenario.