DocumentCode
2901392
Title
Testability features in a high-density memory module
Author
Parrella, Eugene L.
Author_Institution
Fairchild Def., Germantown, MD, USA
fYear
1990
fDate
17-21 Sep 1990
Abstract
A configurable multichip memory module designed in silicon-on-silicon hybrid form is discussed. The memory controller IC, which has been implemented in a CMOS gate array, also functions as an in-circuit tester for the memory chips. This capability, supplemented by the controller´s own scan-path and boundary-scan features, results in increased in-field testability as well as greatly reduced production test costs
Keywords
CMOS integrated circuits; built-in self test; hybrid integrated circuits; integrated circuit testing; ASIC memories; CMOS gate array; MCM; Si on Si hybrid IC; Si-Si; boundary-scan features; configurable multichip memory module; controller´s own scan-path; high-density memory module; in-circuit tester; in-field testability; memory chips; memory controller IC; reduced production test costs; silicon-on-silicon hybrid form; testability features; Assembly; Circuit testing; Delay effects; Integrated circuit testing; Multichip modules; Performance evaluation; Pins; Read-write memory; Sequential analysis; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1990.186104
Filename
186104
Link To Document