Title :
A development system for an SRAM-based user-reprogrammable gate array
Author :
Shibata, Yoshiaki ; Funatsu, Hideyo ; Ishida, Yoshihiro ; Yoshida, Jun
Author_Institution :
LSI Res. Center, Kawasaki Steel Corp., Chiba, Japan
Abstract :
This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries
Keywords :
development systems; logic CAD; logic arrays; ASIC memories; SRAM based FPGA; SRAM-based user-reprogrammable gate array; design editor; development system; functional description entries; general schematic entries; logic block interconnect architecture; minute logics; schematic entry; supports hierarchical designs; Combinational circuits; Field programmable gate arrays; Flip-flops; Hardware; Integrated circuit interconnections; Logic arrays; Logic devices; Power system interconnection; Programmable logic arrays; Programmable logic devices;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186105
