Low cost TMS320C40/XC6200 based re-configurable parallel image processing architecture

To improve the performance and develop a low cost reconfigurable computer, an existing TMS320C40 MIMD processing engine is to be upgraded with additional hardware resources, consisting of four Xilinx XC6200 series field programmable gate arrays (FPGAs). These devices will provide the new hybrid architecture with additional run-time reconfigurable processing, memory and routing resources. Furthermore, the new system will provide a platform for the development of adaptive routing structures, self-configuration techniques and the investigation in the merging of instruction and hardware based parallelism