DocumentCode
2901534
Title
The architecture constraints in test equipment designs
Author
Van Nierop, John
Author_Institution
Hercules Def. Electron. Syst. Inc., Clearwater, FL, USA
fYear
1990
fDate
17-21 Sep 1990
Abstract
The trends in technology and those issues that might prevent the industrial and defense bases from being successful at an affordable cost are discussed. The deficiencies in current automatic test equipment (ATE) designs are illustrated using the VLSI design and test process as an example. Future test technology requirements and a proposed solution are proposed
Keywords
VLSI; automatic test equipment; digital integrated circuits; integrated circuit testing; logic testing; production testing; ATE design deficiencies; VLSI design/test process; architecture constraints; automatic test equipment; solution; test equipment designs; test technology requirements; trends in technology; Circuit testing; Costs; Integrated circuit technology; Military computing; Process design; System testing; Test equipment; Timing; Very high speed integrated circuits; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location
Rochester, NY
Type
conf
DOI
10.1109/ASIC.1990.186114
Filename
186114
Link To Document