Title :
Efficient timing analysis for general synchronous and asynchronous circuits
Author :
Chu, Yuan-Hua ; Liou, Yih-June ; Chen, Jong-Leih
Author_Institution :
Electron. Res. & Service Organ., Hsinchu, Taiwan
Abstract :
After partitioning the circuit into a set of clock groups, an event-driven approach is used to find paths with delays greater than a given threshold value. False paths detected during event propagation are reported to the user. In addition to breaking asynchronous loops dynamically, the tool also checks setup/hold time and minimum pulse width violations in a multiple clock environment. Experimental results are shown to demonstrated the efficiency and effectiveness of the proposed algorithms
Keywords :
VLSI; combinatorial circuits; digital integrated circuits; logic CAD; sequential circuits; asynchronous circuits; breaking asynchronous loops; circuit partitioning; event propagation; event-driven approach; find paths with delays; hold time checks; minimum pulse width violations; multiple clock environment; setup time checks; synchronous circuits; timing analysis; Algorithm design and analysis; Analytical models; Asynchronous circuits; Circuit simulation; Clocks; Flip-flops; Information analysis; Partitioning algorithms; Space vector pulse width modulation; Timing;
Conference_Titel :
ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE
Conference_Location :
Rochester, NY
DOI :
10.1109/ASIC.1990.186120
