Modeling strategy for post layout verification

Author

Navabi, Zainrrlabedin ; Dube, John ; Huang, A.

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

1990

fDate

17-21 Sep 1990

Abstract

Guidelines for the development of portable switch-level VHDL gate models that can be extracted from netlists or layout files are presented. Using these models, a simulation model for a cell-based design can be obtained. The VHDL descriptions of the gates will properly model timing and loading effects. Modeling techniques and procedures for assembling larger models are presented

Keywords

circuit layout CAD; logic CAD; specification languages; VHDL descriptions; assembling larger models; cell-based design; guidelines; layout files; loading effects; modeling strategy; netlists; portable switch-level VHDL gate models; post layout verification; simulation model; timing effects modeling; Capacitance; Circuit simulation; Computational modeling; Data mining; Guidelines; Integrated circuit interconnections; Portable computers; Switches; Timing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Seminar and Exhibit, 1990. Proceedings., Third Annual IEEE

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/ASIC.1990.186123

Filename

186123

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2901667